Low Power System on Chip Implementation Scheme of Digital Filtering Cores

The paper describes a scheme for the implementation of low power cores for hearing aid applications. Power saving features of the scheme are two fold. The first due to the utilisation of a macro-component framework which allows the rapid assembly of the cores on easy-to-verify hierarchical plug-in basis. The second is due to the system-on-chip strategy. The cores are embedded within an ARM-based system-on-chip platform. For this VSIA compliant wrapper interfaces have been investigated which allow the cores operation in multiple clock and bus domains. This provides effective power manipulation by power management strategies. The paper demonstrates the scheme with a number of FIR filtering cores. The cores are assembled with a number of different macro-components from the wide range available within a rich library which contains a flexible and synthesisable set of components for computation, memory, decision, and BIST functions.